Due to the isolation provided by its transformer, a flyback switching power converter is typically selected as the power adapter for portable electronic devices. In particular, the transformer in a flyback converter safely isolates the load from the AC mains. A controller regulates the switching of a power switch over successive power cycles to regulate the output voltage of a flyback converter. The power switch is in series with a primary winding of a transformer so that when it is switched on, a primary current builds up magnetic energy in the transformer. While the primary current flows, the secondary winding must be prevented from conducting current. An output diode may rectify the secondary current to prevent it from flowing while the power switch is cycled on. Such synchronous rectification needs no control but the output diode is lossy such that efficiency suffers. It is thus conventional to increase efficiency by replacing the output diode with a synchronous rectifier (SR) switch transistor.
An SR controller on the secondary side of the transformer monitors a voltage (for example, the drain-to-source voltage) of the SR switch transistor to determine when the power switch transistor has cycled off so that the SR switch transistor may then be cycled on. But the drain-to-source (VD-S) voltage across the SR switch transistor is subject to noise such as from associated electrostatic discharge (ESD) circuitry. The resulting noise on the VD-S voltage can cause the SR controller to switch on the SR switch transistor while the primary switch is still on, resulting in large output currents and possible system damage. It is thus conventional to filter the VD-S voltage to prevent glitches on the VD-S voltage from improperly triggering an on-cycle for the SR switch transistor. But such deglitch filtering delays the on-time for normal cycles of the SR switch transistor, which lowers efficiency.
Operation with and without a deglitch filter may be better understood with reference to the waveforms shown in FIG. 1. From a time t0 to a time t1, the gate voltage (S1 gate) of a power switch transistor is pulsed high for a power cycle with a deglitch filter having a relatively long delay. A secondary current is prevented from flowing during this time. The VD-S voltage across the SR switch transistor pulses high from time t0 to time t1. At time t1, the cycling off of the power switch transistor S1 causes the VD-S voltage to drop below an SR on threshold voltage for switching on the SR switch transistor. In the absence of a deglitch filter, an output of a turn-on comparator comparing the VD-S voltage to the SR on threshold voltage would pulse high at time t1. But the deglitch filter delays the VD-S voltage to provide a filtered output voltage to the turn-on comparator. The output of the turn-on comparator thus does not pulse high until a time t2. The deglitch filter thus introduces a turn-on deglitch delay from time t1 until time t2. In response to the pulsing high of the turn-on comparator output signal, the SR gate voltage for the SR switch transistor is pulsed high at a time t3 shortly after time t2. While the SR switch transistor is on, the VD-S voltage increases until it passes an SR off threshold voltage at a time t4 (the transformer reset time) such that the SR switch transistor is cycled off. The VD-S voltage then begins to resonantly oscillate. At time t1, the secondary current pulses high and then ramps down to zero at time t4.
At a time t5, noise on the VD-S voltage such as resulting from ESD circuitry cause a sharp decrease in the VD-S voltage so that the SR on threshold is momentarily crossed. But the deglitch filtering of the VD-S voltage prevents the turn-on comparator from pulsing its output signal so that the glitch in the VD-S voltage is harmless. At a time t6, another cycle of the power switch transistor S1 begins with a pulsing high of the S1 gate voltage until a time t7, when the power switch transistor S1 is cycled off. But in this power cycle, there is no deglitch filtering such that the turn-on comparator output signal pulses high at time t7. The SR switch is then cycled on so that the secondary current again pulses high and ramps down to zero at a time t8 when the VD-S voltage crosses the SR off threshold voltage so that the SR switch transistor is cycled off. The VD-S voltage again begins to resonantly oscillate. At a time t9, the S1 gate voltage is again pulsed high to begin another power switch cycle. But a glitch on the VD-S voltage at time t9 also causes the SR gate voltage to be pulsed high such that the secondary current quickly ramps to a dangerous level due to the SR switch transistor being on while the power switch transistor S1 is on. Operation without the deglitch filter is more efficient due to the rapid response to the cycling off of the power switch transistor S1 but comes with such a risk of catastrophic failure of the flyback converter.
There is thus a need in the art for improved synchronous rectification for switching power converters offering increased efficiency while still being robust to noise-induced glitches.